R. T. Howe (Spring 1993)
(a) [2 points] Draw the differential half circuit for Stage 1.
(b) [4 points] Draw the differential two-port small-signal model for Stage 1 and find the numerical values of its parameters.
(d) [4 points] Find the numberical value of the small-signal gain vo/s.
(f) [2 points] What is the minimum DC common-mode input voltage, VCM,min, for wich all devvices are forward active (BJT) or saturated (MOS)?
(g) [2 points] What is the DC power dissipation for this amplifier?
A MOS C-V curve is shown above for an n+ polysilicon gate and a p-type substrate, with Na=1E-16 cm¯ ³.
(a) [5 points] Sketch below the C-V curve for this structure when the oxide thickness tox is reduced. Your plot should be qualitatively correct -- the original C-V curve is reproduced to make comparison easier.
(b) [5 points] Sketch below the C-V curve for the complemenatary structure, for which the gate is p+ polysilicon and the substrate is n-type with Na=1E-16 cm¯ ³. Your plot should be qualitatively correct -- the original C-V curve is reproduced to make comparison easier.
n+=0.55 V, surface potential s=(x=0)=0V, x=0 corresponds to the oxide/silicon interface.
(d) [5 points] Sketch the electrostatic potential throught the original structure when VG=2V
(a) [4 points] Find the DC voltages at the drain of M2 and at the source of M 2.
(b) [4 points] Find the small-signal voltage gain avo=vo/vs at low frequencies (consider Cc open).
(d) [4 points] Find the frequency for which the magnitude of the small-signal voltage gain |av|dB=0dB. If you couldn't solve part (b), assume that avo=14,000.
(e) [4 points] Given that the channel length of all MOSFETSs is L=3 µ m and that the oxide capacitance per unit area is Cvo=14,000.
(d) [4 points] Given that the channel length of all MOSFETs is L=3 µ m and that the oxide capacitance per unit area is Cox=0.5 fF/µ m² (1 fF=1E-15 F), find the differential imput capacitance of this op amp.
(a) [4 points] What logic function is implemented by this dynamic logic gate? Use the + sign for "OR", a dot for "AND", and an oversocre for "NOT". There is no need to simplify the expression. Hint: transistor M1 fuctions to "pre-ground" the load capacitance CL, using clock waveform (t).
(b) [4 points] How short a 5-V clock pulse (length T) can be used to pre-gound the load capacitance, assuming that the minimum T is 5 times the propagation delay found in discharaging CL from 5 V ot 0 V? Hint: consider the appropriate transistor to be saturated in finding the propagation delay.
. You are given that vE(0¯ )=5 V just before the clock transitions to 5 V at t=0.(d) [4 points] What is the propagation delay for the situation in part (c) (all inputs low when the clock goes low)? You can consider that M2 is so wide that it fuctions as a short-circuit when it's "on".
(e) [4 points] What is the propagation delay when A, B, D = 0 and C = 1 (5 V) when the clock (t) goes low? If you couldn't solve part (c), assume that its answer was tp=1 ns.
(a) [4 points] Redraw the schematic, replacing all transistor current sources by the current-source symbol (with the numerical value indicated) and all transistor voltage sources by batteries (with the numberical value indicated).
(b) [4 points] What is the numerical value of the input resistance Ri of this current amp?
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(d) [4 points] What is the short-circuit current gain Ai (vo a small-signal short to ground) for this current amplifier? Draw the two-port model for the amp.
(e) [4 points] What is the overall current gain io/iin with the 100 k
load resistor connected to the amplifier?
