Problem #1
Fill in ROM contents in hexadecimal. (Binary answers will receive no credit):
| Address Data | Address Data | Address Data | Address Data |
| 0 1 | 8 9 | 10 11 | 18 19 |
| 2 3 | A B | 12 13 | 1A 1B |
| 4 5 | C D | 14 15 | 1C 1D |
| 6 7 | E F | 16 17 | 1E 1F |
Problem #2
| Present State Q1 Q0 | Input EN | Output SIGNAL | Next State Q1 Q0 |
| 0 0 0 0 | 0 1 | 1 1 | 0 0 0 1 |
| 0 1 0 1 | 0 1 | 0 0 | 0 0 1 1 |
| 1 0 1 0 | 0 1 | 1 0 | 1 1 0 0 |
| 1 1 1 1 | 0 1 | 1 0 | 1 0 1 1 |
Problem #3
| micro-PC address | OUT 15 | OUT12 MEMCS | OUT11 MEMWE | OUT9..10 load grp 1 | OUT6..8 load grp 2 | OUT3..5 output enab | OUT0..2 ALU func |
| 0x20 | 1 | 0 | 0 | NOP | SLOAD | R3OUT | A plus 1 |
| 0x21 | 1 | 0 | 0 | MARLD | NOP | R2OUT | x |
| 0x22 | 1 | 1 | 1 | NOP | NOP | SOUT | x |
| 0x23 | 1 | 0 | 1 | NOP | NOP | SOUT | x |
| 0x24 | 1 | 0 | 0 | NOP | SLOAD | R2OUT | A plus 1 |
| 0x25 | 1 | 0 | 0 | NOP | R2LOAD | SOUT | x |
| 0x26 | 1 | 0 | 0 | MARLD | NOP | R3OUT | x |
| 0x27 | 1 | 1 | 0 | NOP | R3LOAD | NOP | x |
| 0x28 | 1 | 0 | 0 | NOP | NOP | NOP | x |
ALU function table:
| ALU operation | ALU code | ALU operation | ALU code |
| Y = A plus B | 000 | Y = A | 100 |
| Y = A plus B plus carry | 001 | Y = 0 | 101 |
| Y = A plus 1 | 010 | Y = 1 | 110 |
| Y = A minus 1 | 011 | Y = -1 | 111 |
3a. Determine the register transfer description for the
micro-operations corresponding to each line of the micro-program
listed above, and fill in the following table:
| micro-PC address | register transfer description |
| 0x20 | |
| 0x21 | |
| 0x23 | |
| 0x24 | |
| 0x25 | |
| 0x26 | |
| 0x27 |
3b. If R3 is the CPU program counter, and R2 is used
as the stack pointer, describe, in 10 words or less, the computer
instruction corresponding to the above micro-program:
3c. Complete the timing diagram for the micro-instructions 0x24 through 0x27 (defined in table above). For the Data_Bus, show when the bus is tri-stated, and table what is on the bus, e.g. "r2".
Problem #4
| Symbols | Explanations |
| tclock | clock period |
| tskew | clock skew to R2 |
| tsetup, thold | setup and hold times for '377 |
| tDQmax, tDQmin | max. and min. prop. delay from rising edge of clock to Q valid |
| tZAmax, tZAmin | max. and min. time for '125 to become active (= propagation delay) |
| tAZmax, tAZmin | max. and min. time for '125 to become tri-state |
| tcountmax, tcountmin | time from rising edge of clock to '163 outputs |
| tread | time from CS asserted and address valid until RAM data out valid |
| tWEZmax, tWEZmin | time from write enable asserted to RAM data out tri-stated |
| twrite, twritehold | min. time for WE after data is valid, data hold time after WE not asserted |
Answer each part independently. The operation of the RAM is similar to the 2114 studied in lab 5. The control signal MEMCS.L is always asserted.
a. Explain, using register transfer notation, the data transfers taking place in each clock cycle.
b. What is the minimum tclock for R2 to be correctly written with
the contents of R1?
tclock > ___ ?
c. What is the minimum tclock for R2 to be correctly written with
the contents of RAM?
tclock > ___ ?
d. What conditions must be satisfied to ensure that thold for
R2 is not violated?
thold < ___ ?
e. What conditions must be satisfied to ensure that the hold
time for the RAM is not violated during the write cycle?
twritehold < ___ ?
f. There is a potential bus conflict at the beginning of a memory write cycle if the RAM output becomes tri-stated too late. What condition must be satisfied to avoid a bus conflict at this time?
Problem #5
